The definitive guide to the ARM Cortex-M3
(eBook)

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Published
Burlington, MA : Newnes/Elsevier, ©2010.
Format
eBook
Edition
2nd ed.
ISBN
185617963X, 9781856179638, 9781856179645, 1856179648
Physical Desc
1 online resource (xxii, 457 pages) : illustrations
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Language
English

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Bibliography
Includes bibliographical references and index.
Description
The Definitive Guide to the ARM Cortex-M3.
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O'Reilly,O'Reilly Online Learning: Academic/Public Library Edition

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Citations

APA Citation, 7th Edition (style guide)

Yiu, J. (2010). The definitive guide to the ARM Cortex-M3 (2nd ed.). Newnes/Elsevier.

Chicago / Turabian - Author Date Citation, 17th Edition (style guide)

Yiu, Joseph. 2010. The Definitive Guide to the ARM Cortex-M3. Newnes/Elsevier.

Chicago / Turabian - Humanities (Notes and Bibliography) Citation, 17th Edition (style guide)

Yiu, Joseph. The Definitive Guide to the ARM Cortex-M3 Newnes/Elsevier, 2010.

MLA Citation, 9th Edition (style guide)

Yiu, Joseph. The Definitive Guide to the ARM Cortex-M3 2nd ed., Newnes/Elsevier, 2010.

Note! Citations contain only title, author, edition, publisher, and year published. Citations should be used as a guideline and should be double checked for accuracy. Citation formats are based on standards as of August 2021.

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f7e0479f-3bcd-d98d-c829-3c4f1f033ff7-eng
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Grouped Work IDf7e0479f-3bcd-d98d-c829-3c4f1f033ff7-eng
Full titledefinitive guide to the arm cortex m3
Authoryiu joseph
Grouping Categorybook
Last Update2023-12-11 15:41:25PM
Last Indexed2024-03-29 04:16:05AM

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MARC Record

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504 |a Includes bibliographical references and index.
5050 |a Front Cover; Half Title Page; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1. Introduction; 1.1 What Is the ARM Cortex-M3 Processor?; 1.2 Background of ARM and ARM Architecture; 1.2.1 A Brief History; 1.2.2 Architecture Versions; 1.2.3 Processor Naming; 1.3 Instruction Set Development; 1.4 The Thumb-2 Technology and Instruction Set Architecture; 1.5 Cortex-M3 Processor Applications; 1.6 Organization of This Book; 1.7 Further Reading; Chapter 2. Overview of the Cortex-M3.
5058 |a 2.1 Fundamentals2.2 Registers; 2.2.1 R0-R12: General-Purpose Registers; 2.2.2 R13: Stack Pointers; 2.2.3 R14: The Link Register; 2.2.4 R15: The Program Counter; 2.2.5 Special Registers; 2.3 Operation Modes; 2.4 The Built-In Nested Vectored Interrupt Controller; 2.4.1 Nested Interrupt Support; 2.4.2 Vectored Interrupt Support; 2.4.3 Dynamic Priority Changes Support; 2.4.4 Reduction of Interrupt Latency; 2.4.5 Interrupt Masking; 2.5 The Memory Map; 2.6 The Bus Interface; 2.7 The MPU; 2.8 The Instruction Set; 2.9 Interrupts and Exceptions; 2.9.1 Low Power and High Energy Efficiency.
5058 |a 2.10 Debugging Support2.11 Characteristics Summary; 2.11.1 High Performance; 2.11.2 Advanced Interrupt-Handling Features; 2.11.3 Low Power Consumption; 2.11.4 System Features; 2.11.5 Debug Supports; Chapter 3. Cortex-M3 Basics; 3.1 Registers; 3.1.1 General Purpose Registers R0 through R7; 3.1.2 General Purpose Registers R8 through R12; 3.1.3 Stack Pointer R13; 3.1.4 Link Register R14; 3.1.5 Program Counter R15; 3.2 Special Registers; 3.2.1 Program Status Registers; 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers; 3.2.3 The Control Register; 3.3 Operation Mode; 3.4 Exceptions and Interrupts.
5058 |a 3.5 Vector Tables3.6 Stack Memory Operations; 3.6.1 Basic Operations of the Stack; 3.6.2 Cortex-M3 Stack Implementation; 3.6.3 The Two-Stack Model in the Cortex-M3; 3.7 Reset Sequence; Chapter 4. Instruction Sets; 4.1 Assembly Basics; 4.1.1 Assembler Language: Basic Syntax; 4.1.2 Assembler Language: Use of Suffixes; 4.1.3 Assembler Language: Unified Assembler Language; 4.2 Instruction List; 4.2.1 Unsupported Instructions; 4.3 Instruction Descriptions; 4.3.1 Assembler Language: Moving Data; 4.3.2 LDR and ADR Pseudo-Instructions; 4.3.3 Assembler Language: Processing Data.
5058 |a 4.3.4 Assembler Language: Call and Unconditional Branch4.3.5 Assembler Language: Decisions and Conditional Branches; 4.3.6 Assembler Language: Combined Compare and Conditional Branch; 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions; 4.3.8 Assembly Language: Saturation Operations; 4.4 Several Useful Instructions in the Cortex-M3; 4.4.1 MSR and MRS; 4.4.2 More on the IF-THEN Instruction Block; 4.4.3 SDIV and UDIV; 4.4.4 REV, REVH, and REVSH; 4.4.5 Reverse Bit; 4.4.6 SXTB, SXTH, UXTB, and UXTH; 4.4.7 Bit Field Clear and Bit Field Insert; 4.4.8 UBFX and SBFX.
520 |a The Definitive Guide to the ARM Cortex-M3.
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